`default_nettype none

module test_rst_m (
    input  rst_w_ni,
    input  clk_w_i,

    output led_green_w_no,
    output led_red_w_no
);
    reg rst_r_nl;
    reg prev_rst_r_nl;
    reg led_red_r_nl;
    reg led_green_r_nl;

    initial begin
        led_red_r_nl   <= 1;
        led_green_r_nl <= 1;
    end

    always @(posedge clk_w_i) begin
        if (rst_r_nl == 0) begin
            led_red_r_nl <= 0;
        end
        if (prev_rst_r_nl == 1 && rst_r_nl == 0) begin
            led_green_r_nl <= 0;
        end
        prev_rst_r_nl <= rst_r_nl;
        rst_r_nl <= rst_w_ni;
    end

    assign led_green_w_no = led_green_r_nl;
    assign led_red_w_no = led_red_r_nl;
endmodule
